ISIS SCHEMATIC FILE07/03/0519/09/13K,B5;R  DESIGN CONFIGURATION DATAArialDefault Font p \E M ``@@@@ COMPONENTȪȪPINPORT@MARKER`O@ACTUATOR`O INDICATOR`O@@VPROBE`OIPROBE`OTAPE`O GENERATOR`OTERMINAL@ SUBCIRCUIT=ȪȪ 2D GRAPHICWIRE DOT@@@WIRE@BUS WIREPSPanelȪSUBCKT= COMPONENT ID&H Default FontCOMPONENT VALUE&0 Default Font PROPERTIES&0 Default FontTERMINAL LABEL&0 Default Font WIRE LABEL&H Default Font SUBCKT ID&H Default Font SUBCKT NAME&0 Default FontSCRIPT&0 Default FontPIN NAME&0 Default Font PIN NUMBER&0 Default Font VPROBE LABEL&0 Default Font IPROBE LABEL&0 Default FontGENERATOR LABEL&0 Default Font TAPE LABEL&0 Default FontACTIVE READOUT0ArialCOMPONENT TEXT&0 Default Font DESCRIPTION& Default Font GRAPHICS TEXT&0 Default Font SUB HEADING& Default Font $MKRDECREMENT:70!`OACTUATOR;4!`OACTUATOR9ȜȜ;4!`OACTUATOR98cȜ;4!`OACTUATOR9p $MKRINCREMENT:70!`OACTUATOR;4!`OACTUATORpȜ8c;4!`OACTUATORp8c8c;4!`OACTUATORp9$MKRNODE޳3~94`O@MARKER9pp994`O@MARKER99pp $MKRORIGIN{3=8`O@MARKER9p s94`O@MARKER s94`O@MARKER s $MKRPINNAME޳304$MKRORIGINje`O@MARKER0Default FontNAME $MKRPINNUM޳304$MKRORIGINhc`O@MARKER/0Default Font99 $PINDEFAULT޳3264PIN?04$MKRORIGIN04?$MKRNODE04$MKRPINNUM04$MKRORIGIN04$MKRPINNAME $PINIECNEGOP364PIN064PIN`04$MKRPINNAME04`$MKRNODE04$MKRORIGIN040$MKRPINNUMZ`PIN4001.IECy J @8"ȪȪCOMPONENT@04$MKRORIGIN<4"ȪȪCOMPONENT`0<4"ȪȪCOMPONENT0(`<4"ȪȪCOMPONENT0%`jb"ȪȪCOMPONENT`p_`3Default Font1 ?$PINIECNEGOPY3 $PINDEFAULTA1 p_$PINDEFAULTB2{*DEVICE} PREFIX=U PINOUT=4001 DATA=cd4001bc.pdf,,,,,Proteus CD,pdfs\digital {*PROPDEFS} {PACKAGE="PCB Package",PACKAGE,2,DIL14,SO14} {MODFILE=LISA Model File,READONLY STRING} {VOLTAGE=Model Timing Voltage:,KWDLIST,3,5V,10V,15V} {ITFMOD=Interface Model,HIDDEN STRING} {*COMPONENT} {PACKAGE=DIL14} {MODFILE=40NOR2} {VOLTAGE=5V} {ITFMOD=CMOS} {*INDEX} {DESC=Quad 2-Input NOR Gate} {CAT=CMOS 4000 series} {SUBCAT=Gates & Inverters} 4011.IECy J W04$MKRORIGIN@8"ȪȪCOMPONENT@jb"ȪȪCOMPONENT`? `3Default Font& ?$PINIECNEGOPY3 $PINDEFAULTA1 p_$PINDEFAULTB2{*DEVICE} PREFIX=U PINOUT=4011 DATA=cd4011bc.pdf,,,,,Proteus CD,pdfs\digital {*PROPDEFS} {PACKAGE="PCB Package",PACKAGE,2,DIL14,SO14} {MODFILE=LISA Model File,READONLY STRING} {VOLTAGE=Model Timing Voltage:,KWDLIST,3,5V,10V,15V} {ITFMOD=Interface Model,HIDDEN STRING} {*COMPONENT} {PACKAGE=DIL14} {MODFILE=40NAND2} {VOLTAGE=5V} {ITFMOD=CMOS} {*INDEX} {DESC=Quad 2-Input NAND Gate} {CAT=CMOS 4000 series} {SUBCAT=Gates & Inverters} 4030.IECy JiP@8"ȪȪCOMPONENT@jb"ȪȪCOMPONENTH? `3Default Font=04$MKRORIGINjb"ȪȪCOMPONENT ? `3Default Font1 $PINDEFAULTA1 p_$PINDEFAULTB2 ?$PINDEFAULTY3{*DEVICE} PREFIX=U PINOUT=4030 DATA=cd4030c.pdf,,,,,Proteus CD,pdfs\digital {*PROPDEFS} {MODFILE=LISA Model File,READONLY STRING} {PACKAGE="PCB Package",PACKAGE,2,DIL14,SO14} {VOLTAGE=Model Timing Voltage:,KWDLIST,3,5V,10V,15V} {ITFMOD=Interface Model,HIDDEN STRING} {*COMPONENT} {PACKAGE=DIL14} {MODFILE=40XOR2} {VOLTAGE=5V} {ITFMOD=CMOS} {*INDEX} {DESC=Quad XOR Gate} {CAT=CMOS 4000 series} {SUBCAT=Gates & Inverters} 4069.IECy J704$MKRORIGIN@8"ȪȪCOMPONENT@jb"ȪȪCOMPONENT`? `3Default Font1 ?$PINIECNEGOPY2 ?$PINDEFAULTA1{*DEVICE} PREFIX=U PINOUT=4069 DATA=cd4069ubc.pdf,,,,,Proteus CD,pdfs\digital {*COMPONENT} {PACKAGE=DIL14} {MODFILE=40INV} {VOLTAGE=5V} {ITFMOD=CMOS} {*PROPDEFS} {VOLTAGE=Model Timing Voltage:,KWDLIST,3,5V,10V,15V} {ITFMOD=Interface Model,HIDDEN STRING} {MODFILE=LISA Model File,READONLY STRING} {PACKAGE=PCB Footprint:,PACKAGE,0} {*INDEX} {DESC=Hex Inverter (Unbuffered)} {CAT=CMOS 4000 series} {SUBCAT=Gates & Inverters} 4077.IECy J4P@8"ȪȪCOMPONENT@04$MKRORIGINjb"ȪȪCOMPONENT ? `3Default Font1jb"ȪȪCOMPONENT3h 3Default Font= $PINDEFAULTA1 p_$PINDEFAULTB2 ?$PINIECNEGOPY3o{*DEVICE} PREFIX=U PINOUT=4077 {*COMPONENT} {MODFILE=40XOR2} {VOLTAGE=5V} {PACKAGE=DIL14} {ITFMOD=CMOS} {*PROPDEFS} {VOLTAGE=Model Timing Voltage:,KWDLIST,3,5V,10V,15V} {ITFMOD=Interface Model,HIDDEN STRING} {MODFILE=LISA Model File,READONLY STRING} {PACKAGE=PCB Footprint:,PACKAGE,0} {*INDEX} {DESC=Quad XNOR Gate} {CAT=CMOS 4000 series} {SUBCAT=Gates & Inverters} 4081.IECy JV04$MKRORIGIN@8"ȪȪCOMPONENT@jb"ȪȪCOMPONENT`? `3Default Font& $PINDEFAULTA1 p_$PINDEFAULTB2 ?$PINDEFAULTY3{*DEVICE} PREFIX=U PINOUT=4081 DATA=cd4081bc.pdf,,,,,Proteus CD,pdfs\digital {*COMPONENT} {PACKAGE=DIL14} {MODFILE=40AND2} {VOLTAGE=5V} {ITFMOD=CMOS} {*PROPDEFS} {VOLTAGE=Model Timing Voltage:,KWDLIST,3,5V,10V,15V} {ITFMOD=Interface Model,HIDDEN STRING} {MODFILE=LISA Model File,READONLY STRING} {PACKAGE=PCB Footprint:,PACKAGE,0} {*INDEX} {DESC=Quad 2-Input AND Gate} {CAT=CMOS 4000 series} {SUBCAT=Gates & Inverters} 7407.IEC2J0@8"ȪȪCOMPONENT@<4"ȪȪCOMPONENTH/x ?<4"ȪȪCOMPONENTx ?HO<4"ȪȪCOMPONENTHOH/04$MKRORIGIN ?$PINDEFAULTA1 ?$PINDEFAULTY2{*DEVICE} PREFIX=U PINOUT=7407 DATA=dm7407.pdf,,,,,Proteus CD,pdfs\digital {*PROPDEFS} {MODFILE=LISA Model File,READONLY STRING} {PACKAGE="PCB Package",PACKAGE,2,DIL14,SO14} {ITFMOD=Interface Model,HIDDEN STRING} {*COMPONENT} {MODFILE=74BUF.MDF} {PACKAGE=DIL14} {ITFMOD=TTL} {*INDEX} {DESC=Hex Buffers / Drivers with Open-Collector High-Vltage Outputs} {CAT=TTL 74 series} {SUBCAT=Buffers & Drivers} 7432.IEC'J<4"ȪȪCOMPONENT9<4"ȪȪCOMPONENTp_9p_04$MKRORIGIN@8"ȪȪCOMPONENT@<4"ȪȪCOMPONENT`0<4"ȪȪCOMPONENT0(`<4"ȪȪCOMPONENT0%`jb"ȪȪCOMPONENT`p_`3Default Font1 $PINDEFAULTA1 p_$PINDEFAULTB2 ?$PINDEFAULTY3F{*DEVICE} PREFIX=U PINOUT=7432 {*PROPDEFS} {MODFILE=LISA Model File,READONLY STRING} {PACKAGE="PCB Package",PACKAGE,2,DIL14,SO14} {ITFMOD=Interface Model,HIDDEN STRING} {*COMPONENT} {MODFILE=74OR2.MDF} {PACKAGE=DIL14} {ITFMOD=TTL} {*INDEX} {DESC=Quad 2-input positive-OR gates} {CAT=TTL 74 series} {SUBCAT=Gates & Inverters} LOGICSTATE H!~`"ȪȪwCOMPONENTO0O00OO0jb"ȪȪCOMPONENT/ `Default Font?04$MKRORIGIN040$MKRINCREMENT0400$MKRDECREMENT$PINDEFAULTQ0LS_0$~`"ȪcCOMPONENTO0O00OO0jb"ȪȪ{COMPONENT/ `Arial004$MKRORIGINLS_1$~`"ȪcCOMPONENTO0O00OO0jb"ȪȪ{COMPONENT/ `Arial104$MKRORIGIN{*DEVICE} ACTIVE=LS,2 {*PROPDEFS} {PRIMITIVE="Primitive Type",HIDDEN STRING} {STATE="Active State",HIDDEN STRING} {*INDEX} {CAT=Debugging Tools} {SUBCAT=Logic Stimuli} {DESC=Logic State Source (Latched Action)} {*COMPONENT} {PRIMITIVE=DIGITAL,RTDSTATE} {STATE=0} {PACKAGE=NULL} [4001]y J*PINOUT 4001 ELEMENTS=4 PINS=14 IP A = 1,5,8,12 IP B = 2,6,9,13 OP Y = 3,4,10,11 PP (VDD) = 14 PP (VSS) = 7 PINSWAP=A,B GATESWAP=TRUE [4011]y J*PINOUT 4011 ELEMENTS=4 PINS=14 IP A = 1,5,8,12 IP B = 2,6,9,13 OP Y = 3,4,10,11 PP (VDD) = 14 PP (VSS) = 7 PINSWAP=A,B GATESWAP=TRUE [4030]y J*PINOUT 4030 ELEMENTS=4 PINS=14 IP A = 1,5,8,12 IP B = 2,6,9,13 OP Y = 3,4,10,11 PP (VDD) = 14 PP (VSS) = 7 PINSWAP=A,B GATESWAP=TRUE [4069]y J{*PINOUT 4069 ELEMENTS=6 PINS=14 IP A = 1,3,5,13,11,9 OP Y = 2,4,6,12,10,8 PP (VDD) = 14 PP (VSS) = 7 GATESWAP=TRUE [4077]y J*PINOUT 4077 ELEMENTS=4 PINS=14 IP A = 1,5,8,12 IP B = 2,6,9,13 OP Y = 3,4,10,11 PP (VDD) = 14 PP (VSS) = 7 PINSWAP=A,B GATESWAP=TRUE [4081]y J*PINOUT 4081 ELEMENTS=4 PINS=14 IP A = 1,5,8,12 IP B = 2,6,9,13 OP Y = 3,4,10,11 PP (VDD) = 14 PP (VSS) = 7 PINSWAP=A,B GATESWAP=TRUE [7407](J{*PINOUT 7407 ELEMENTS=6 PINS=14 IP A = 1,3,5,9,11,13 PD Y = 2,4,6,8,10,12 PP (VCC) = 14 PP (GND) = 7 GATESWAP=TRUE [7432](J*PINOUT 7432 ELEMENTS=4 PINS=14 IP A = 1,4,9,12 IP B = 2,5,10,13 OP Y = 3,6,8,11 PP (VCC) = 14 PP (GND) = 7 PINSWAP=A,B GATESWAP=TRUE NISIS CIRCUIT FILEe& \EOBJECT DATAU1:A[дp2H Default FontCOMPONENT ID4001[P`50 Default FontCOMPONENT VALUE4001[ \10 Default FontSUBCKT NAME.{PACKAGE=DIL14} {MODFILE=40NOR2} {VOLTAGE=5V} [ \00 Default FontPROPERTIES<{PACKAGE=DIL14} {MODFILE=40NOR2} {VOLTAGE=5V} {ITFMOD=CMOS} 4001.IECpepLU2:A[U2H Default FontCOMPONENT ID4011[tE50 Default FontCOMPONENT VALUE4011[ГA10 Default FontSUBCKT NAME/{PACKAGE=DIL14} {MODFILE=40NAND2} {VOLTAGE=5V} [ГA00 Default FontPROPERTIES={PACKAGE=DIL14} {MODFILE=40NAND2} {VOLTAGE=5V} {ITFMOD=CMOS} 4011.IEC DUMU3:A[p2H Default FontCOMPONENT ID4030[ז50 Default FontCOMPONENT VALUE4030[10 Default FontSUBCKT NAME.{PACKAGE=DIL14} {MODFILE=40XOR2} {VOLTAGE=5V} [00 Default FontPROPERTIES<{PACKAGE=DIL14} {MODFILE=40XOR2} {VOLTAGE=5V} {ITFMOD=CMOS} 4030.IECNU4:A[ ֋2H Default FontCOMPONENT ID4077[{50 Default FontCOMPONENT VALUE4077[pw10 Default FontSUBCKT NAME.{MODFILE=40XOR2} {VOLTAGE=5V} {PACKAGE=DIL14} [pw00 Default FontPROPERTIES<{MODFILE=40XOR2} {VOLTAGE=5V} {PACKAGE=DIL14} {ITFMOD=CMOS} 4077.IECOU5:AА2H Default FontCOMPONENT ID4081Аo50 Default FontCOMPONENT VALUE4081АP10 Default FontSUBCKT NAME.{PACKAGE=DIL14} {MODFILE=40AND2} {VOLTAGE=5V} АP00 Default FontPROPERTIES<{VOLTAGE=5V} {ITFMOD=CMOS} {MODFILE=40AND2} {PACKAGE=DIL14} 4081.IEC0?PdF HU7:A[0r:2H Default FontCOMPONENT ID7407[R*50 Default FontCOMPONENT VALUE7407[r&10 Default FontSUBCKT NAME1{MODFILE=74BUF.MDF} {PACKAGE=DIL14} {ITFMOD=TTL} [r&00 Default FontPROPERTIES17407.IEC":RU8:AА1#2H Default FontCOMPONENT ID743250 Default FontCOMPONENT VALUE7432`110 Default FontSUBCKT NAME1{MODFILE=74OR2.MDF} {PACKAGE=DIL14} {ITFMOD=TTL} `100 Default FontPROPERTIES17432.IEC0"S#CDA8@'2H Default FontCOMPONENT IDA8 50 Default FontCOMPONENT VALUE LOGICSTATE810 Default FontSUBCKT NAME'{PRIMITIVE=DIGITAL,RTDSTATE} {STATE=0} 800 Default FontPROPERTIES' LOGICSTATE"T#C@WIRE"p_"B82H Default FontCOMPONENT ID8`150 Default FontCOMPONENT VALUE LOGICSTATE80Q 10 Default FontSUBCKT NAME'{PRIMITIVE=DIGITAL,RTDSTATE} {STATE=0} 80Q 00 Default FontPROPERTIES' LOGICSTATE`UD@WIRE A`p_`80o2H Default FontCOMPONENT ID850 Default FontCOMPONENT VALUE LOGICSTATE8/10 Default FontSUBCKT NAME'{PRIMITIVE=DIGITAL,RTDSTATE} {STATE=0} 8/00 Default FontPROPERTIES' LOGICSTATE?VdF@WIREp_?p_??p_?8p2H Default FontCOMPONENT ID8P50 Default FontCOMPONENT VALUE LOGICSTATE8 10 Default FontSUBCKT NAME'{PRIMITIVE=DIGITAL,RTDSTATE} {STATE=0} 8 00 Default FontPROPERTIES' LOGICSTATEW H@WIRE??p_8 2H Default FontCOMPONENT ID8n50 Default FontCOMPONENT VALUE LOGICSTATE8Ѝ10 Default FontSUBCKT NAME'{PRIMITIVE=DIGITAL,RTDSTATE} {STATE=0} 8Ѝ00 Default FontPROPERTIES' LOGICSTATEXHN @.`wo"ȪȪCOMPONENT[`Default FontRouge : tat 1 @.`vn"ȪȪCOMPONENT[`Default FontBleu : tat 0 `"ȪȪCOMPONENT[`Default FontChoisir les tats logiques ici ""ȪȪCOMPONENT[`Default FontIci, relever l'tat logique en sortie ໪0A"ȪȪCOMPONENT[`Default FontAppuyer sur la touche "Play" en bas pour lancer la simulationU9:AАP2H Default FontCOMPONENT ID4069АЍ50 Default FontCOMPONENT VALUE4069АЍ10 Default FontSUBCKT NAME-{PACKAGE=DIL14} {MODFILE=40INV} {VOLTAGE=5V} АЍ00 Default FontPROPERTIES;{PACKAGE=DIL14} {MODFILE=40INV} {VOLTAGE=5V} {ITFMOD=CMOS} 4069.IEC0]d%HN@WIREp_ISIS CIRCUIT FILE \EOBJECT DATACCT000)6 __DEFAULT__{NROOT10 L/U1:AY3A1B2M0U2:AY3A1B2N1U3:AA1B2Y3O2U4:AA1B2Y3P3U5:AA1B2Y3R5U7:AA1Y2S6U8:AA1B2Y3T7AU8BV9W:X;d<U9:A%Y2A1CCT000 __DEFAULT__ __DEFAULT__ ?40AND2.MDFLISA MODEL DESCRIPTION FORMAT 3.0 ================================= Design: I:\050697\PRODEV\TESTJIGS\CMOS.NEW\40and2.dsn Doc. no.: Revision: Author: Created: 16-Jul-96 Modified: 16-Jul-96 *PROPERTIES,1 TGQ=? *MAPPINGS,3,VALUE+VOLTAGE 4081+5V : TDLHDQ=45n, TDHLDQ=55n 4081+10V : TDLHDQ=20n, TDHLDQ=25n 4081+15V : TDLHDQ=15n, TDHLDQ=20n *MODELDEFS,0 *PARTLIST,1 U2,AND_2,AND_2,PRIMITIVE=DIGITAL,TDHLDQ=,TDLHDQ=,TGQ= *NETLIST,3 A,2 A,IT U2,IP,D0 B,2 B,IT U2,IP,D1 Y,2 Y,OT U2,OP,Q *GATES,0 40INV.MDFLISA MODEL DESCRIPTION FORMAT 6.1 ================================= Design: K:\PROLIBS\DIGITAL\CMOS\40INV.DSN Doc. no.: Revision: Author: Created: 09-Jul-96 Modified: 26/09/01 *PROPERTIES,1 TGQ=? *MAPPINGS,15,VALUE+VOLTAGE 4009+5V : SCHMITT=[NULL], TDHLDQ=35n, TDLHDQ=55n 4009+10V : SCHMITT=[NULL], TDHLDQ=20n, TDLHDQ=25n 4009+15V : SCHMITT=[NULL], TDHLDQ=15n, TDLHDQ=20n 4049+5V : SCHMITT=[NULL], TDHLDQ=35n, TDLHDQ=55n 4049+10V : SCHMITT=[NULL], TDHLDQ=20n, TDLHDQ=25n 4049+15V : SCHMITT=[NULL], TDHLDQ=15n, TDLHDQ=20n 4069+5V : SCHMITT=[NULL], TDHLDQ=45n, TDLHDQ=40n 4069+10V : SCHMITT=[NULL], TDHLDQ=20n, TDLHDQ=20n 4069+15V : SCHMITT=[NULL], TDHLDQ=15n, TDLHDQ=15n 4584+5V : SCHMITT="D", TDHLDQ=220n, TDLHDQ=220n 4584+10V : SCHMITT="D", TDHLDQ=80n, TDLHDQ=80n 4584+15V : SCHMITT="D", TDHLDQ=70n, TDLHDQ=70n 40106+5V : SCHMITT="D", TDHLDQ=220n, TDLHDQ=220n 40106+10V : SCHMITT="D", TDHLDQ=80n, TDLHDQ=80n 40106+15V : SCHMITT="D", TDHLDQ=70n, TDLHDQ=70n *MODELDEFS,0 *PARTLIST,1 U1,INVERTER,INVERTER,PRIMITIVE=DIGITAL,SCHMITT=,TDHLDQ=,TDLHDQ=,TGQ= *NETLIST,2 Y,2 Y,OT U1,OP,Q A,2 A,IT U1,IP,D *GATES,0 40NAND2.MDFLISA MODEL DESCRIPTION FORMAT 6.1 ================================= Design: K:\PROLIBS\DIGITAL\CMOS\40NAND2.DSN Doc. no.: Revision: Author: Created: 09-Jul-96 Modified: 25/09/01 *PROPERTIES,1 TGQ=? *MAPPINGS,6,VALUE+VOLTAGE 4011+5V : SCHMITT=[NULL], TDHLDQ=55n, TDLHDQ=55n 4011+10V : SCHMITT=[NULL], TDHLDQ=25n, TDLHDQ=25n 4011+15V : SCHMITT=[NULL], TDHLDQ=20n, TDLHDQ=20n 4093+5V : SCHMITT="D0,D1", TDHLDQ=90n, TDLHDQ=85n 4093+10V : SCHMITT="D0,D1", TDHLDQ=40n, TDLHDQ=40n 4093+15V : SCHMITT="D0,D1", TDHLDQ=30n, TDLHDQ=30n *MODELDEFS,0 *PARTLIST,1 U1,NAND_2,NAND_2,PRIMITIVE=DIGITAL,SCHMITT=,TDHLDQ=,TDLHDQ=,TGQ= *NETLIST,3 Y,2 Y,OT U1,OP,Q A,2 A,IT U1,IP,D0 B,2 B,IT U1,IP,D1 *GATES,0 ?40NOR2.MDFLISA MODEL DESCRIPTION FORMAT 3.0 ================================= Design: I:\050697\PRODEV\TESTJIGS\CMOS.NEW\40nor2.dsn Doc. no.: Revision: Author: Created: 09-Jul-96 Modified: 29-Jul-96 *PROPERTIES,1 TGQ=? *MAPPINGS,3,VALUE+VOLTAGE 4001+5V : TDHLDQ=65n, TDLHDQ=40n 4001+10V : TDHLDQ=30n, TDLHDQ=20n 4001+15V : TDHLDQ=25n, TDLHDQ=15n *MODELDEFS,0 *PARTLIST,1 U?,NOR_2,NOR_2,PRIMITIVE=DIGITAL,TDHLDQ=,TDLHDQ=,TGQ= *NETLIST,3 Y,2 Y,OT U?,OP,Q A,2 A,IT U?,IP,D0 B,2 B,IT U?,IP,D1 *GATES,0 40XOR2.MDFLISA MODEL DESCRIPTION FORMAT 6.1 ================================= Design: K:\PROLIBS\DIGITAL\CMOS\40XOR2.DSN Doc. no.: Revision: Author: Created: 09-Jul-96 Modified: 26/09/01 *PROPERTIES,1 TGQ=? *MAPPINGS,9,VALUE+VOLTAGE 4030+5V : TDHLDQ=85n, TDLHDQ=75n, INVERT=[NULL] 4030+10V : TDHLDQ=35n, TDLHDQ=30n, INVERT=[NULL] 4030+15V : TDHLDQ=30n, TDLHDQ=25n, INVERT=[NULL] 4070+5V : TDHLDQ=85n, TDLHDQ=75n, INVERT=[NULL] 4070+10V : TDHLDQ=30n, TDLHDQ=30n, INVERT=[NULL] 4070+15V : TDHLDQ=35n, TDLHDQ=25n, INVERT=[NULL] 4077+5V : TDHLDQ=75n, TDLHDQ=70n, INVERT=Q 4077+10V : TDHLDQ=35n, TDLHDQ=30n, INVERT=Q 4077+15V : TDHLDQ=30n, TDLHDQ=25n, INVERT=Q *MODELDEFS,0 *PARTLIST,1 U?,XOR_2,XOR_2,INVERT=,PRIMITIVE=DIGITAL,TDHLDQ=,TDLHDQ=,TGQ= *NETLIST,3 Y,2 Y,OT U?,OP,Q A,2 A,IT U?,IP,D0 B,2 B,IT U?,IP,D1 *GATES,0 74BUF.MDFLISA MODEL DESCRIPTION FORMAT 3.0 ================================= Design: 74BUF.DSN Doc. no.: Revision: Author: Created: 10-Aug-93 Modified: 03-Mar-94 *PROPERTIES,1 TGQ=? *MAPPINGS,3 7407 : TDLHDQ=6n, TDHLDQ=20n, OCOPS=Q 7417 : TDLHDQ=6n, TDHLDQ=20n, OCOPS=Q 74HC07 : TDLHDQ=7n, TDHLDQ=7n, OCOPS=Q *MODELDEFS,0 *PARTLIST,1 U2,BUFFER,BUFFER,OCOPS=,PRIMITIVE=DIGITAL,TDHLDQ=,TDLHDQ=,TGQ= *NETLIST,2 A,2 A,IT U2,IP,D Y,2 Y,OT U2,OP,Q 74INV.MDFLISA MODEL DESCRIPTION FORMAT 6.1 ================================= Design: K:\PROLIBS\DIGITAL\TTL\74INV.DSN Doc. no.: Revision: Author: Created: 02-Aug-93 Modified: 04/12/01 *PROPERTIES,1 TGQ=? *MAPPINGS,16,VALUE 74HC04 : TDLHDQ=9n, TDHLDQ=9n, SCHMITT=[NULL], OCOPS=[NULL] 74HC05 : TDLHDQ=11n, TDHLDQ=9n, SCHMITT=[NULL], OCOPS=Q 74HC14 : TDLHDQ=14n, TDHLDQ=14n, SCHMITT=D, OCOPS=[NULL] 74HCT04 : TDLHDQ=11n, TDHLDQ=11n, SCHMITT=[NULL], OCOPS=[NULL] 74HCU04 : TDLHDQ=6n, TDHLDQ=6n, SCHMITT=[NULL], OCOPS=[NULL] 74LS04 : TDLHDQ=9n, TDHLDQ=10n, SCHMITT=[NULL], OCOPS=[NULL] 74LS05 : TDLHDQ=17n, TDHLDQ=15n, SCHMITT=[NULL], OCOPS=Q 74LS14 : TDLHDQ=15n, TDHLDQ=15n, SCHMITT=D, OCOPS=[NULL] 74LS19 : TDLHDQ=13n, TDHLDQ=18n, SCHMITT=[NULL], OCOPS=[NULL] 74S04 : TDLHDQ=3n, TDHLDQ=3n, SCHMITT=[NULL], OCOPS=[NULL] 74S05 : TDLHDQ=5n, TDHLDQ=4.5n, SCHMITT=[NULL], OCOPS=Q 7404 : TDLHDQ=12n, TDHLDQ=8n, SCHMITT=[NULL], OCOPS=[NULL] 7405 : TDLHDQ=40n, TDHLDQ=8n, SCHMITT=[NULL], OCOPS=Q 7406 : TDLHDQ=10n, TDHLDQ=15n, SCHMITT=[NULL], OCOPS=Q 7414 : TDLHDQ=15n, TDHLDQ=15n, SCHMITT=D, OCOPS=[NULL] 7416 : TDLHDQ=10n, TDHLDQ=15n, SCHMITT=[NULL], OCOPS=Q *MODELDEFS,0 *PARTLIST,1 U3,INVERTER,INVERTER,OCOPS=,PRIMITIVE=DIGITAL,SCHMITT=,TDHLDQ=,TDLHDQ=,TGQ= *NETLIST,2 A,2 A,IT U3,IP,D Y,2 Y,OT U3,OP,Q *GATES,0 <74OR2.MDFLISA MODEL DESCRIPTION FORMAT 3.0 ================================= Design: 74OR2.DSN Doc. no.: Revision: Author: Created: 03-Aug-93 Modified: 03-Mar-94 *PROPERTIES,1 TGQ=? *MAPPINGS,5 7432 : TDLHDQ=10n, TDHLDQ=14n 74HC32 : TDLHDQ=8n, TDHLDQ=8n 74HCT32 : TDLHDQ=13n, TDHLDQ=13n 74LS32 : TDLHDQ=14n, TDHLDQ=14n 74S32 : TDLHDQ=4n, TDHLDQ=4n *MODELDEFS,0 *PARTLIST,1 U2,OR_2,OR_2,PRIMITIVE=DIGITAL,TDHLDQ=,TDLHDQ=,TGQ= *NETLIST,3 A,2 A,IT U2,IP,D0 B,2 B,IT U2,IP,D1 Y,2 Y,OT U2,OP,Q {ITFMOD.MDFLISA MODEL DESCRIPTION FORMAT 5.0 ================================= Design: K:\Prodev\Spice\ITFMOD.DSN Doc. no.: Revision: Author: Created: 18/03/98 Modified: 23/06/05 *MODELDEFS,18 CMOS : RHI=100,RLO=100,TRISE=1u,TFALL=1u,V+=VDD,V-=VSS NMOS : RHI=100,RLO=10,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,V+=VCC,V-=GND TTL : RHI=50, RLO=5,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,RPOS=5k,RNEG=20k,V+=VCC,V-=GND,FLOAT=HIGH TTLHC : RHI=5,RLO=5, V+=VCC,V-=GND TTLHCT : RHI=5,RLO=5, V+=VCC,V-=GND TTLLS : RHI=100, RLO=10,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,RPOS=12k,RNEG=50k, V+=VCC,V-=GND,FLOAT=HIGH TTLS : RHI=25, RLO=2.5,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,RPOS=5k,RNEG=20k,TRISE=0.5n,TFALL=0.5n, V+=VCC,V-=GND,FLOAT=HIGH PLD : RHI=20,RLO=20, V+=VCC,V-=GND,FLOAT=HIGH PIC : RSHI=20, RSLO=20,RWHI=20k,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,V+=VDD,V-=VSS,TRISE=10n,TFALL=10n PIC3V3 : RSHI=20, RSLO=20,RWHI=20k,VUD=2,VTL=0.8,VHL=0.1,VTH=1.5,VHH=0.1,V+=VDD,V-=VSS,TRISE=10n,TFALL=10n 8051 : RHI=20, RLO=20,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,RPOS=5k,RNEG=20k,V+=VCC,V-=GND,FLOAT=HIGH,TRISE=10n,TFALL=10n AT89 : RHI=20, RLO=20,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,RPOS=5k,RNEG=20k,V+=VCC,V-=GND,FLOAT=HIGH,TRISE=10n,TFALL=10n HC11 : RHI=20, RLO=20,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,V+=VDD,V-=VSS,TRISE=10n,TFALL=10n AVR : RSHI=20, RSLO=20,RWHI=100k,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,V+=VCC,V-=GND,TRISE=10n,TFALL=10n MSP430 : RSHI=20, RSLO=20,RWHI=100k,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,V+=VCC,V-=GND,TRISE=10n,TFALL=10n LPC2100: RSHI=20, RSLO=20,RWHI=100k,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,V+=V3,V-=VSS BSTAMP : RSHI=20, RSLO=20,RWHI=20k,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,V+=VDD,V-=VSS,TRISE=10n,TFALL=10n RS232 : VLO=-8.5,VHI=8.5,RHI=300,RLO=300,VTL=1.2,VHL=0.5,VTH=1.7,VHH=0.5,RPOS=5k,RNEG=5k,V+=VCC,V-=GND,FLOAT=HIGH,TRISE=1u,TFALL=1u ???@ư>,ABSTOL1e-012 BADMOS3No BYPASSYesCHGTOL1e-014 CONLOG2DEFAD0DEFAS0 DEFL0.0001 DEFW0.0001 GLEAK1e-012 GMIN1e-012GMINSTEPS100 ITL1100ITL250ITL410 LOGSTART0 LOGTIME60 MAXORD2 METHODGEAR NOOPITERNoNUMSTEPS50000 OLDLIMITNo PIVREL0.001PIVTOL1e-013 RELTOL0.001 SRCSTEPS10 TDLOWER0.9 TDSCALE1 TDUPPER1.1TEMP27 TMIN1e-018TNOM27TRACE_CONTENTIONS1,0TRACE_CONVERGENCE1,1TRACE_DCPATHS1,2TRACE_ITFMODS1,3TRACE_NETTYPES1,4TRACE_OPTIONS1,5TRACE_PERFORMANCE1,6TRACE_SPICELINK1,7TRTOL7TRYTOCOMPACTNo TTOL1e-006 VNTOL1e-006@vQ6>"`0MսI &0